With the continuous progress of a manufacturing process, there are more and more transistors inside a chip, an in-chip system becomes more and more complicated, dozens of or even hundreds of Internet Protocol (IP) cores are integrated usually, and the inter-core communication is one of the main problems of SOC design. The complicated system adopts a shared interconnection system in a standard generally.
In a complicated shared interconnection system, all communications may be converted into storage accesses to each other. The party that sends a storage access request is a master device, and the party that receives the storage access request is a slave device. An SOC is a system for connecting multiple master devices and slave devices.
In the current shared interconnection system, each master device has a bus Identifier (ID). The ID has two functions: 1, for routing when a response to the access request is returned; and 2, due to different IDs, the master devices are enabled to not receive the responses in a sending order, and a matrix or a crossbar may forward requests or responses out of order according to practical conditions when transferring the requests or the responses. The matrix or the crossbar is collectively referred to as an interconnection matrix herein.
However, bit widths of the IDs are increased with progressive increase of interconnection depths, which results in increase of bus protocol overheads, high power consumption and high cost payout. Secondly, interconnection of bus with different ID widths may be implemented by means of ID conversion (ID conversion through an adaptor), so as to result in increase of access delays, influence on design, verification, backend implementation and the like, and adverseness to power consumption and cost control.